1. Field of the Invention:
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of fabricating an electrode structure having an increased surface area for a double-crown type of capacitor in a dynamic random-access memory (DRAM) device.
2. Description of Related Art:
In IC fabrication, the primary goal is to make the resulting IC device as highly integrated as possible. To achieve this goal, the various semiconductor components in the IC device should be sized as small as possible in accordance with the design rules. In the case of DRAM, however, the downsizing of the device would also reduce the size of its data storage capacitor, and hence reduce the capacitance of the capacitor, resulting in a reduced data retaining capability by the capacitor. A DRAM capacitor with a smaller capacitance would require more frequent refreshing of the data stored therein, and thus would be more power consumptive and less reliable to operate. One solution to increase the capacitance is to use a capacitor called a stacked capacitor, in which the electrodes are formed in a stacked manner with a special dielectric film sandwiched therebetween. This type of capacitor, however, is still provides inadequate capacitance.
Another solution is to use a capacitor known as a trench-type capacitor, in which a trench structure with a thin dielectric film is formed to provide an increased surface area for the electrodes. This solution, however, would cause low yield rate and low reliability in DRAM production.
Presently, many 3-dimensional types of capacitors have been proposed to increase the capacitance of the DRAM capacitor. One example is U.S. Pat. No. 5,399,518, granted to Sim et al., which discloses a method for fabricating a double-cylindrical type of capacitor. In this capacitor, the electrode is formed in a double-cylindrical shape including an inner cylindrical structure and an outer cylindrical structure to allow a large surface area for the electrode to provide an increased capacitance.
Another example is U.S. Pat. No. 5,443,993, granted to Part et al., which discloses another method for fabricating a double-cylindrical type of capacitor through the formation of a provisional insulating spacer structure that is later removed to provide the desired electrode structure.
Moreover, U.S. Pat. No. 5,491,103, granted to Aho et al., discloses another method for fabricating a double-cylindrical type of capacitor, which is characterized in the use of low-temperature oxide as a sidewall structure to the photoresist layer for the purpose of preventing the photoresist layer from being deformed during the process.
Even further, U.S. Pat. No. 5,438,013, granted to Kim et al., discloses another method for fabricating a double-cylindrical type of capacitor, which is characterized in the use of controlled undercut to form a double-sidewall mask used to define the electrodes.
As to the stacked capacitor, its capacitance can be increased by increasing the height of the stacked cells in the memory cell region of the DRAM device. One drawback to this solution, however, is that, when the stacked cells are higher than the peripheral region of the DRAM device, cell planarization and the forming of metal interconnects are more difficult to carry out. Therefore, at the deep-submicron level of integration, there still exists a need for a new method for the fabrication of a DRAM capacitor having a large capacitance.